Category: Projects

This is a follow-up post to my previous project page Part 5 (PC software).

This is the last post concerning this project. I have done some tests with the final hardware and software. Furthermore I have written a small conclusion to this project.

Transient response

An interesting test is the transient response on a sudden change of the setpoint current. In this case I stepped the setpoint current from 2 A to 0 A. The following picture shows the voltage across the shunt. You can see a voltage drop of 200 mV (corresponding to 2 A) within a time span of around 20 ms. The time could be reduced by decreasing C18 and C21 in the schematic. The latter one should be adjusted carefully because a too small capacitor may destabilise the control loop.

This is a follow-up post to my previous project page Part 2 (Hardware design details).

In this post I briefly present the full schematic and PCB layout of this project. As a proof that I actually built this device, there are also some pictures included at the end of the post. 😉

Full schematic and PCB layout

The schematic and layout has been drawn with KiCad 4. The full schematic is attached below (as PNG image, PDF and KiCad’s native format). The layout is not depicted in this post, it should be opened with KiCad directly for clarity.

Active Load v1 schematic (PDF version)

ActiveLoad v1 KiCad files (including PCB layout)

You can also find the latest version of the schematic and the PCB in my GitHub repository.

Pictures of the finished device

Read further on as I describe the firmware part of the project in part 4.

This is a follow-up post to my previous project page Part 1 (Requirements).

In the last part I laid out the requirements and specifications of my active load without going too much into detail. This is about to change while I write about the different implementation details.

The main task of the active load is – of course – to dissipate power. This can be done by any device which has resistance. The simplest load is just a resistor but the problem is that a resistor usually has a fixed resistance which makes no sense in an active load. So we need a device which can dissipate (a lot of) power and has a controllable resistance. This can be done with a power transistor or in this particular case with a power FET. The idea is to control the gate-source voltage in order to influence the drain-source resistance. The device under test is just connected to drain and source.

This time I would like to write about a project of mine: A (simple) active load with support from a microcontroller.

There are times when you need a dummy load to test and validate some equipment or part of a schematic, e.g. a power supply. In the past I just used some power resistors as a load but this solution is very inflexible. Often you don’t have the right resistors at hand or you must switch resistors when you want to change the simulated load.

It would be nice to have a simple and cheap active load which solves the above problems. My design approach relies on the great Re:load 2 project by Arachnid Labs. I added a STM32 microcontroller with USB support and LCD to my own design. This way I can use my active load as a standalone device which shows me all important pieces of information on the display. Or I can connect a computer via USB to the device and let the PC control and monitor the simulated load.

Here are the requirements:

• Power supply from around 3.3V to 40V
• Should be powered by device under test
• Alternative power supply via USB
• Maximum dissipated power: Around 12W permanently at room temperature
• Maximum current: 3A
• Robust (protected from overvoltage, overcurrent and overtemperature conditions)
• Device under test should be connected via banana plugs or screw terminals
• A PC should be able to monitor the actual current and control the desired current via USB
• Small display to monitor actual and setpoint current
• Rotary encoder to change setpoint current
• Small (5×10 cm)
• Measure temperature at heatsink

Read further on as I write about the hardware design details in part 2.