This is a follow-up post to my previous project page Part 1 (Requirements).
In the last part I laid out the requirements and specifications of my active load without going too much into detail. This is about to change while I write about the different implementation details.
The main task of the active load is – of course – to dissipate power. This can be done by any device which has resistance. The simplest load is just a resistor but the problem is that a resistor usually has a fixed resistance which makes no sense in an active load. So we need a device which can dissipate (a lot of) power and has a controllable resistance. This can be done with a power transistor or in this particular case with a power FET. The idea is to control the gate-source voltage in order to influence the drain-source resistance. The device under test is just connected to drain and source.